1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a thin film transistor array substrate and a fabricating method thereof that are adaptive for simplifying processing as well as assuring reliability. The present invention also is directed to a liquid crystal display panel having the thin film transistor array substrate and a fabricating method thereof.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls light transmittance of a liquid crystal using an electric field to thereby display a picture. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix type, and a driving circuit for driving the liquid crystal display panel.
The liquid crystal display panel includes a thin film transistor array substrate and a color filter array substrate opposed to each other, a liquid crystal injected between two substrates, and a spacer for keep a cell gap between two substrates.
The thin film transistor array substrate consists of gate lines, data lines, thin film transistors formed as switching devices for each intersection between the gate lines and the data lines, pixel electrodes formed for each liquid crystal cell and connected to the thin film transistor, and alignment films coated thereon. The gate lines and the data lines receive signals from the driving circuits via each pad portion. The thin film transistor applies a pixel signal fed to the data line to the pixel electrode in response to a scanning signal fed to the gate line.
The color filter array substrate consists of color filters formed for each liquid crystal cell, black matrices for dividing color filters and reflecting an external light, common electrodes for commonly applying reference voltages to the liquid crystal cells, and an alignment film coated thereon.
The liquid crystal display panel is completed by preparing the thin film array substrate and the color filter array substrate individually to join them and then injecting a liquid crystal between them and sealing it.
In such a liquid crystal display, the thin film transistor substrate has a complicated fabrication process that is a major factor in increasing the manufacturing cost of the liquid crystal display panel. The fabrication process both involves a semiconductor process and needs a plurality of mask process. In order to decrease the manufacturing cost, a reduction in the number of mask processes when fabricating the thin film transistor substrate is desirable. Each mask process includes a number of individual processes such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping and inspection processes, etc. Until recently, the standard fabrication process involved five mask processes. However, a fabrication process containing four mask processes has been developed.
FIG. 1 is a plan view illustrating a thin film transistor array substrate adopting a four mask process, and FIG. 2 is a section view of the thin film transistor array substrate taken along the I-I′ line in FIG. 1.
Referring to FIG. 1 and FIG. 2, the thin film transistor array substrate includes a gate line 2 and a data line 4 provided on a lower substrate 42 to intersect each other with having a gate insulating film 44 therebetween, a thin film transistor 6 provided at each intersection, and a pixel electrode 18 provided at a cell area having a crossing structure. Further, the thin film transistor array substrate includes a storage capacitor 20 provided at an overlapped portion between the pixel electrode 18 and the pre-stage gate line 2, a gate pad portion 26 connected to the gate line 2, and a data pad portion 34 connected to the data line 4.
The thin film transistor 6 allows a pixel signal applied to the data line 4 to be charged into the pixel electrode 18 and kept in response to a scanning signal applied to the gate line 2. To this end, the thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, a drain electrode 12 connected to the pixel electrode 18, and an active layer 14 overlapping with the gate electrode 8 and defining a channel between the source electrode 10 and the drain electrode 12.
The active layer 14 overlapping with the source electrode 10 and the drain electrode 12 and having a channel portion between the source electrode 10 and the drain electrode 12 also overlaps with the data line 4, a lower data pad electrode 36 and a storage electrode 22. On the active layer 14, the data line 4, the source electrode 10, the drain electrode 12, the lower data pad electrode 36, the storage electrode 22 and an ohmic contact layer 48 are further provided.
The pixel electrode 18 is connected, via a first contact hole 16 passing through a protective film 50, to the drain electrode 12 of the thin film transistor 6. The pixel electrode 18 generates a potential difference with respect to a common electrode provided at an upper substrate (not shown) by the charged pixel voltage. This potential difference rotates a liquid crystal positioned between the thin film transistor substrate and the upper substrate owing to dielectric anisotropy of the liquid crystal and transmits light inputted, via the pixel electrode 18, from a light source (not shown) toward the upper substrate.
The storage capacitor 20 consists of a pre-stage gate line 2, a storage electrode 22 overlapping with the gate line 2 having the gate insulating film 44, the active layer 14 and the ohmic contact layer 48 therebetween, and a pixel electrode 22 overlapping with the storage electrode 22 having the protective film 50 therebetween and connected via a second contact hole 24 defined at the protective film 50. The storage capacitor 20 allows a pixel signal charged in the pixel electrode 18 to be stably maintained until the next pixel voltage is charged.
The gate line 2 is connected, via the gate pad portion 26, to a gate driver (not shown). The gate pad portion 26 consists of a lower gate pad electrode 28 extended from the gate line 2, and an upper gate pad electrode 32 connected, via a third contact hole 30 passing through the gate insulating film 44 and the protective film 50, to the lower gate pad electrode 28.
The data line 4 is connected, via the data pad portion 34, to the data driver (not shown). The data pad portion 34 consists of a lower data pad electrode 36 extended from the data line 4, and an upper data pad electrode 40 connected, via a fourth contact hole 38 passing through the protective film 50, to the lower data pad electrode 36.
Hereinafter, a method of fabricating the thin film transistor substrate having the above-mentioned structure adopting the four mask process will be described in detail with reference to FIG. 3A to FIG. 3D.
Referring to FIG. 3A, gate metal patterns including the gate line 2, the gate electrode 8 and the lower gate pad electrode 28 are provided on the lower substrate 42 by the first mask process.
More specifically, a gate metal layer is formed on the lower substrate 42 by a deposition technique such as sputtering. Then, the gate metal layer is patterned by photolithography and etching using a first mask to thereby form gate metal patterns including the gate line 2, the gate electrode 8 and the lower gate pad electrode 28. The gate metal layer has a single-layer or double-layer structure of chrome (Cr), molybdenum (Mo) or an aluminum group metal, etc.
Referring to FIG. 3B, the gate insulating film 44 is coated onto the lower substrate 42 provided with the gate metal patterns. Further, a semiconductor pattern including the active layer 14 and the ohmic contact layer 48 and source/drain metal patterns including the data line 4, the source electrode 10, the drain electrode 12, the lower data pad electrode 36 and the upper storage electrode 22 are provided on the gate insulating film 44 by the second mask process.
More specifically, the gate insulating film 44, an amorphous silicon layer, a n+ amorphous silicon layer and a source/drain metal layer are sequentially provided on the lower substrate 42 provided with the gate metal patterns by deposition techniques such as plasma enhanced chemical vapor deposition (PECVD) and sputtering, etc. Herein, the gate insulating film 44 is formed from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). The source/drain metal is selected from molybdenum (Mo), titanium (Ti), tantalum (Ta) or a molybdenum alloy, etc.
Then, a photo-resist pattern is formed on the source/drain metal layer by photolithography using a second mask. In this case, a diffractive exposure mask having a diffractive exposing part at a channel portion of the thin film transistor is used as a second mask, thereby allowing a photo-resist pattern in the channel portion to have a lower height than the photo-resist pattern in the source/drain pattern portions.
Subsequently, the source/drain metal layer is patterned by wet etching using the photo-resist pattern to thereby provide the source/drain metal patterns including the data line 4, the source electrode 10, the drain electrode 12 being integral to the source electrode 10 and the storage electrode 22.
Next, the n+ amorphous silicon layer and the amorphous silicon layer are patterned at the same time by dry etching using the same photo-resist pattern to thereby provide the ohmic contact layer 48 and the active layer 14.
The photo-resist pattern having a relatively low height is removed from the channel portion by ashing and thereafter the source/drain metal pattern and the ohmic contact layer 48 of the channel portion are dry etched. Thus, the active layer 14 of the channel portion is exposed to disconnect the source electrode 10 from the drain electrode 12.
Then, the photo-resist pattern left on the source/drain metal pattern group is removed by stripping.
Referring to FIG. 3C, the protective film 50 including the first and fourth contact holes 16, 24, 30 and 38 are formed on the gate insulating film 44 provided with the source/drain metal patterns.
More specifically, the protective film 50 is formed on the entire gate insulating film 44 provided with the source/drain metal patterns by a deposition technique such as PECVD. Then, the protective film 50 is patterned by photolithography and etching using a third mask to thereby define the first to fourth contact holes 16, 24, 30 and 38. The first contact hole 16 passes through the protective film 50 and exposes the drain electrode 12, whereas the second contact hole 24 passes through the protective film 50 and exposes the storage electrode 22. The third contact hole 30 passes through the protective film 50 and the gate insulating film 44 and exposes the lower gate pad electrode 28. The fourth contact hole 38 passes through the protective film 50 and exposes the upper data pad electrode 36.
The protective film 50 is made from an inorganic insulating material identical to the gate insulating film 44, or an organic insulating material such as an acrylic organic compound having a small dielectric constant, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane), etc.
Referring to FIG. 3D, transparent conductive film patterns including the pixel electrode 18, the upper gate pad electrode 32 and the upper data pad electrode 40 are provided on the protective film 50 by the fourth mask process.
A transparent conductive film is deposited over the entire protective film 50 by a deposition technique such as sputtering, etc. Then, the transparent conductive film is patterned by photolithography and etching using a fourth mask to thereby provide the transparent conductive film patterns including the pixel electrode 18, the upper gate pad electrode 32 and the upper data pad electrode 40. The pixel electrode 18 is electrically connected, via the first contact hole 16, to the drain electrode 12 while being electrically connected, via the second contact hole 24, to the storage electrode 22 overlapping with the pre-stage gate line 2. The upper gate pad electrode 32 is electrically connected, via the third contact hole 30, to the lower gate pad electrode 28. The upper data pad electrode 40 is electrically connected, via the fourth contact hole 38, to the lower data pad electrode 36. Herein, the transparent conductive film is formed from indium-tin-oxide (ITO), tin-oxide (TO) or indium-zinc-oxide (IZO).
As described above, the conventional thin film transistor array substrate and the fabricating method thereof as mentioned above uses four mask processes, thereby reducing the number of fabricating processes and hence a manufacturing cost in comparison with fabrication techniques using a five mask process. However, since the four mask process still has a complicated fabricating process which limits the cost reduction, it is desirable to simplify the fabricating process to further reduce the manufacturing cost.